1. Field of the Invention
The present invention relates to a dot clock synchronization generator circuit which can be applied, for example, to LSIs (integrated circuits) for processing video signals.
2. Description of the Related Art
Some LSI for processing video signals generates a video clock synchronized with an external video clock within the LSI. Such an LSI is not applied with an external video clock but is applied only with external video signal and horizontal synchronization signal (EXHSYNC) to generate a clock having the same frequency and phase as the external video clock based on an oscillation clock at a higher frequency than the video clock applied from the outside (hereinafter called the “high frequency clock”) and the horizontal synchronization signal, such that external video signals are processed by this internally generated clock. The internally generated clock is used for processing external video signals instead of the external video clock because of such advantages as the ability to execute part of video processing in accordance with the high frequency clock, and elimination of wiring for supplying the video clock to the LSI.
In the generation of the video clock (hereinafter called the “dot clock” which particularly refers to an internally generated clock), for matching the frequency between the dot clock and the external video clock, a frequency division ratio from the high frequency clock to the dot clock may be previously set by a register or the like. Also, as mentioned above, the horizontal synchronization signal EXHSYNC is applied from the outside for matching the phase of the dot clock with the phase of the external video clock. Within the LSI, the applied external horizontal synchronization signal EXHSYNC is also handled as a horizontal synchronization signal HSYNC as it is.
A video processing system which includes an LSI as described above must maintain a relationship between the number of rising edges (or the number of falling edges) of the external video clock generated after the external horizontal synchronization signal EXHSYNC falls and the number of rising edges (or the number of falling edges) of the dot clock generated inside after the horizontal synchronization signal HSYNC falls, as shown in FIG. 2. This is because the number of rising edges represents the positions of pixels on an associated horizontal line in the horizontal direction, and the number of pixels on a horizontal line and the order of pixels from the left end of the horizontal line are counted within a video processing circuit contained in the LSI.
The dot clock, though generated to have the same frequency and the same phase as the external video clock, is a self-running clock generated within the LSI, so that it is basically asynchronous to the external video clock. For this reason, the two clocks can shift larger from each other gradually over time unless a synchronization feature is provided. A timing at which the LSI is applied with the external horizontal synchronization signal EXHSYNC synchronized with the external video clock for synchronizing the dot clock to the external video clock is also asynchronous for the LSI. Therefore, when the dot clock is adjusted in phase based on the external horizontal synchronization signal EXHSYNC, a hazard (a clock pulse having a pulse width equal to or smaller than that allowed by the device) can introduce into a dot clock sequence depending on an input timing relationship between the dot clock and the external horizontal synchronization signal EXHSYNC, possibly resulting in a malfunction of a device which receives the dot clock sequence.
Here, a synchronizing method applied to the dot clock must maintain the relationship between the number of rising edges of the dot clock internally generated after the falling of the horizontal synchronization signal HSYNC and the number of rising edges of the external video clock generated after the falling of the external horizontal synchronization signal EXHSYNC.
Therefore, a need exists for a dot clock synchronization generator circuit which is capable of generating a dot clock that is in synchronism with an external video signal which can ensure a pulse width allowed by a device which is supplied with the dot clock (and preferably capable of ensuring a predetermined number of clocks per horizontal scanning line).